1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and more particularly, to a semiconductor device having a polymetal gate structure and a method of manufacturing the device.
2. Background Art
The steps of forming a gate electrode on a semiconductor substrate have been conventionally carried out according to the following procedure (see, for example, Japanese Laid-open Patent Application No. 2002-188401).
Initially, a gate insulating film and a polysilicon layer are successively formed on a semiconductor substrate in which a diffusion layer has been formed, followed by thermal treatment to facilitate the crystallization of the polysilicon layer. Next, a tungsten nitride layer, a tungsten layer and a silicon oxide film are successively formed on the polysilicon layer. The tungsten nitride layer serves as a barrier layer for suppressing the reaction between the polysilicon layer and the tungsten layer. Thereafter, a resist film is formed on the silicon oxide film and patterned by lithography, followed by further patterning of the silicon oxide film through the mask of the resultant resist pattern. Subsequently, using the silicon oxide film pattern as a hard mask, the tungsten layer, tungsten nitride layer, polysilicon layer and gate insulating layer are, respectively, etched. Thereafter, after formation of a silicon oxide film, this film is etched back over the entire surface thereof to form side walls. According to the steps set out hereinabove, a gate electrode is formed on the semiconductor substrate.
However, where a constituent material for the gate electrode is exposed to high heating temperatures (of 950° C. or over, for example) in such gate electrode-forming steps and also in subsequent steps, a problem has arisen in that a high resistance layer, such as a silicon nitride film or silicon oxide film, is formed at the interface between the polysilicon layer and the tungsten nitride layer. The presence of the high resistance layer has made it difficult to permit the good ohmic contact of the gate electrode, with the attendant problem that failures, such as a work failure or delay of a semiconductor device, are caused.